Key words
digital systems, VHDL, RTL-design, asynchronous design
Objectives
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To become acquainted with high-level hardware description languages, i.e. VHDL;
- Learn how to design at RTL-level;
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Analysis and design of asynchonous circuits
Topics
Theory
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Boolean expressions and logic gates. Two- en multilayer implementations. Karnaugh-diagrams en minimalisation algorithmes.
- Hardware description languages. Introduction to VHDL.
- Commonly used combinatoric circuits and their VHDL description: adders, binary multipliers, multiplexers, demultiplexers, encoders, decoders.
- Synchronous sequential logic. Latches and flipflops. Analysis of sequential circuits.
- State reduction. Synthesis of sequential circuits. VHDL-description.
- Often used sequential circuits and their VHDL-description: registers, shift registers, ripple counters, synchronous counters.
- RTL-design. Datapath model. Algorithmic state machines (ASM). VHDL-description of FSM and ASM. Different methodologies for designing control logic.
- Asynchronous logic. Analysis of asynchronous logic. Circuits with latches.
Design of asynchronous logic. Reduction of state and flow tables.
Race-free state assignment. Hazards.
Laboratory
The lab sessions are tightly linked to the theory: the design of several basic circuits, simulations in VHDL, implementations on CPLDs and FPGAs, the use of a logic state analyser.
Prerequisites
Digital electronics I
Final Objectives
After following this course the student should be able to simulate, design and test complex digital circuits in a high-level hardware description language. To this end three necessary skills are being taught: design at RTL-level with ASMs, programming and simulation in VHDL, analysis of asynchronous phenomena.
Materials used
Teacher's courses + school library materials
Study costs
Study guidance
The teaching staff can be contacted via the course site for questions and comments.
If necessary additional appointments can be made.
Teaching Methods
Lectures illustrated with laboratory sessions.
Assessment
Theory: Oral examination with course notes available
Laboratory: Permanent evaluation
A weighted average is used to compute the final score for a training item.
However, if a student gains a score of 7 or less on 20 on one of the different courses
(parts of training items) , he proves that his skill for certain subcompetencies is
insufficient. Consequently, one can turn from the arithmetical calculation of the final
assignment of quotas of a training item and the new marks can be awarded on consensus.
Of course, the examiners can judge that the arithmetic regulations mentioned in the
study index card can also be used for 7 or less.
For each deviation a detailed motivation ought to be drawn up. In that case one should
point out that the skill for this subcompetency is proven to be insufficient,
if the student didn’t pass the partim that is considered to be important
for certain subcompetencies.
Lecturer(s)
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