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ONTWERP VAN INGEBEDDED SYSTEMEN I |
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| Taught in |
1st year Master in Industrial Sciences in Electronics-ICT - Main Subject: ICT
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| Theory |
[A] 24.0 |
| Exercises |
[B] 12.0 |
| Training and projects |
[C] 0.0 |
| Studytime |
[D] 85.0 |
| Studypoints |
[E] 3 |
| Level |
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| Credit contract? |
Access upon approval |
| Examination contract? |
Access upon approval |
| Language of instruction |
Dutch |
| Lecturer |
Peter Veelaert
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| Reference |
IMIWEI01A00004 |
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Key words
Objectives
Topics
1. Register transfers and datapaths
2. Sequencing and control
3. Memories
4. A processor Architecture
5. VHDL-implementation of a processor
6. Combinatoric optimalisation of reconfigurable hardware
7. Datapath optimalisation and dataflowgraphs (DFGs)
8. Testability
Prerequisites
Final Objectives
Materials used
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Study costs
Study guidance
Teaching Methods
Assessment
Lecturer(s)
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